Embodiments of the present invention relate to memory technology, and more particularly to the handling of read operations in a memory.
Various memory technologies exist. Semiconductor memories are used in many systems including servers, personal computers, cellular telephones, personal digital assistants (PDAs), portable media players and the like. Many systems use multiple memories, including random access memories, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), and other memories, such as flash memories. Flash memory is a high-speed electrically erasable programmable read only memory (EEPROM) in which erasing and programming is performed on blocks of data.
Different types of flash memories exist, including flash memories based on NOT-OR (NOR) technology and NOT-AND (NAND) technology. These different types of flash memory have different characteristics. Typically, NOR-based flash designs read a single data group from memory at a time. A second read cannot be initiated until the prior read is latched out of the memory. The first data word is available after a short latency or delay. Subsequent data words follow at a rate determined by the clock frequency. Accordingly, NOR-based flash devices are often used for code storage, and more particularly for storage of code used for execute-in-place (XIP) operation. In contrast, NAND-based flash devices have a long latency before data is available from the device, and such NAND devices are suitable for data storage applications.
Oftentimes it is unsuitable to use multiple memories for both code and data storage. Accordingly, a need exists for improved memory technologies.